The present invention relates to semiconductor integrated circuits and, more specifically, to a digitally-programmable delay line for use in a multi-phase clock generator, for example.
Multi-phase clock generators have been used in semiconductor integrated circuits for a variety of different applications. One common application of a multi-phase clock generator is in telecommunications equipment for capturing data received from high-speed Asynchronous Transfer Mode (ATM) Wide Area Networks (WAN) and Local Area Networks (LAN), for example. The phase of the input data is compared with each available phase output from the clock generator. The phase output having a falling edge that coincides with the data edges is selected to control latches, which acquire the input data, in order to place the rising edge as close to the center of the data eye as possible.
A typical multi-phase clock generator generates clock signals which are equally distributed in phase over 360 degrees. An analog phase-locked loop (PLL) or ring oscillator is typically used to generate the clock signals. While analog PLLs can generate multiple clock signals that are substantially equally distributed in phase, these circuits have several disadvantages. For example if the reference clock input to the PLL stops, the PLL loses phase lock, which must be re-established when the reference clock returns. Also, analog PLL circuits are relatively sensitive to noise and interference. Analog PLLs can also be difficult to test during design and manufacturing verification.
An alternative to analog multi-phase clock generators is therefore desired, which is capable of maintaining phase lock when the reference clock stops, is easy to test, can maintain a constant duty cycle across all phases, and is relatively insensitive to changes in process, voltage and temperature.
One embodiment of the present invention is directed to a digitally programmable delay circuit, which includes a control input and a plurality of delay stages coupled in series with one another to form a delay line. Each stage has a previous stage input, a previous stage output, a next stage input and a next stage output. The next stage output and the next stage input are coupled to the previous stage input and the previous stage output, respectively, of a next one of the delay stages in the delay line. The previous stage input is coupled to the next stage output. The previous stage input and the next stage input are selectively coupled to the previous stage output based on the control input.
Another embodiment of the present invention is directed to a digital multi-phase clock generator. The clock generator includes a reference clock input, a plurality of delay outputs having different phases from one another, and a plurality of programmable delay circuits coupled to the reference clock input, in series with one another. Each delay circuit generates one of the delay outputs and comprises a delay control input, a programmable delay, and an input load that is independent of the programmable delay. A phase detector and a delay control circuit are coupled to the plurality of delay circuits to form a digital phase-locked loop, which locks a phase of one of the delay outputs to a phase of the reference clock input. The delay control circuit has a digital delay control output coupled to the delay control inputs of the delay circuits.